The present invention concerns a testable power-on-reset circuit which allows for the test of reset features of an electronic device without the requirement that power be removed from the electronic device.
In many electronic devices, a power-on-reset circuit is included. The power-on-reset circuit detects when the electronic device on which the power-on-reset circuit resides is powered up. Once the power-on-reset circuit detects power up of the electronic device, the power-on-reset circuit holds its output low for a period of time sufficient for the entire electronic device to receive full power-up. While the power-on-reset circuit holds its output low, the electronic device performs a reset. After the entire electronic device has received full power up, the power-on-reset raises its output high, at which time the electronic device completes the reset sequence.
Electronic devices are typically tested using automatic test equipment (ATE). Often times it is desirable for an ATE to loop through a number of test vectors, each of the test vectors beginning with a reset of the electronic device. Such vector looping is an important debugging and characterization procedure which is performed with power constantly applied to the electronic device under test. Unfortunately, use of a conventional power-on-reset circuit does not allow such vector looping because an electronic device including a conventional power-on-reset circuit does not issue a reset without the removing and then re-applying of power to the electronic device.